1. Field of the invention
This invention relates to a semiconductor integrated circuit which receives electrical power at different direct current voltages. More particularly, the invention relates to a semiconductor integrated circuit for preventing deterioration of or damage to elements due to abnormal currents that can occur in a transient state, when a direct current is turned on and off in a semiconductor integrated circuit.
2. Description of the Prior art
It has been made possible to integrate a plurality of functions, implemented by several semiconductor circuits, into one semiconductor device or one monolithic semiconductor integrated circuit, by the introduction of the large scale semiconductor integrated circuit. Thus, the number of parts and size has decreased, and price and electrical power consumption have been lowered, while performance has been improved. This trend is accelerating, and much effort is being made to remove even one part from an electrical device. By integrating as many functions as possible into one semiconductor device, the number of electrical parts has been reduced.
In the past, semiconductor devices with different constructions were produced on respective independent substrates. Thus, the reduction in the number of parts has been limited. However, semiconductor devices having different constructions, such as identical substrate Bi-CMOS (Bipolar-Complementary Metal Oxide Semiconductor) are easily produced at the present time. In this way, a large scale integrated circuit (LSI) has become of use with the advantages of bipolar transistors, such as analog processing ability, high current driving ability, and high speed operation and also the advantages of CMOS, such as high density integration and low power consumption, which helps to achieve the objects described above. However, in the case of an analog-digital hybrid circuit, such as a Bi-CMOS circuit, a CMOS logic circuit normally requires a positive power source, an analog circuit normally requires both positive and negative power supplies, and bipolar ECL (Emitter Coupled Logic) normally requires a negative power source for a reference potential, Vref. Generally, an input-output voltage of a CMOS logic circuit requires a positive voltage, an input-output voltage of an analog circuit requires both positive and negative voltages, and an input-output voltage of an ECL circuit requires a negative voltage. In a case like this where constructions and circuit systems differ, it is impossible to drive respective circuits with a single voltage, and it is necessary to provide power supplies with a different polarity or voltages compared to the reference potential Vref, according to circuit requirements.
FIGS. 11A-11F show a circuit block integrated into a single semiconductor circuit substrate. FIGS. 11A-11C show cases of a p-type substrate, and FIGS. 11D-FIG. 11F show cases of an n-type substrate. In FIGS. 11A-11F, frames drawn with dotted lines show portions of a semiconductor integrated circuit on the same substrate. A positive voltage +Vdd and a negative voltage -Vss, compared to the reference potential Vref, are supplied from the outside. Circuits 1, 2, and 3 are CMOS circuits, other MOS circuits, and logic circuits or analog circuits, including ECL bipolar elements, as described above.
In the past, in semiconductor integrated circuits that receive electrical power from the different DC (direct current) voltage power sources, compared to the reference potential Vref, and use the reference potential Vref, there have been cases in which the on-off sequence of the different power sources had to be decided prior to use. In addition, when the on-off sequence of the different power sources cannot be assigned, some measures are needed between the power source circuit and the semiconductor Integrated circuit.
When semiconductor integrated circuits are formed on one silicon substrate, even in the described BI-CMOS semiconductor integrated circuit, circuit elements on a p-type silicon substrate are mutually connected inside the circuit. The method normally used to isolate the Integrated circuits is a pn junction. In this method, elements are normally isolated by applying a reverse bias voltage to a pn junction. If a p-type (or an n-type) silicon substrate is employed in order to apply the reverse bias voltage to the pn junction, a minimum electric potential (or a maximum electric potential) is given to the substrate. If this condition cannot be satisfied, a parasitic circuit is secondarily activated in the designed elements. In a CMOS circuit, the activation causes latch-up, and excessive current flows into elements and wires and may cause deterioration or breakage. In the case of a bipolar circuit, activation of a parasitic element causes heating in labyrinthine circuits, sometimes causing deterioration of or damage to elements. In recent years, design technology has improved, and latch-up and deterioration of or damage to the elements has become rare. However, since the construction potentially Includes the phenomenon described above, depending on the on-off sequence of different power sources, protection is needed when the circuits are turned on or turned off.
FIG. 12 shows a sectional view of a simple Bi-CMOS Integrated circuit in a p-type substrate of a semiconductor integrated circuit. In FIG. 12 the circuit comprises internal electrical elements, power supplies providing voltages +Vdd and -Vss, and switches S1 and S2, which turn on or off the power source current, an input "in 1" of the CMOS circuit and an input "In 2" of the bipolar circuit. FIGS. 13A and 13B show electrical equivalent circuits of the structure of FIG. 12. Unimportant resistors and other elements are omitted in FIGS. 12, 13A, and 13B. In FIGS. 12, 13A, and 13B, p channel transistors T1 and n channel transistors T2 form the CMOS circuit, and npn transistors T3 and resistors R4 and RS, formed by diffusion, form the bipolar circuits. In FIGS. 13A and 13B, the single dot dashed line shows the designed circuit and the double dot dashed line shows the parasitic circuits. In FIGS. 13A and 13B, transistors Q1, Q2, Q3, Q4, and Q5, and resistors R1, R2, R3, and R4 are secondary parasitic elements. The application of the power supply voltages to these parasitic circuits is explained below.
FIG. 13A shows a normal case where the switch S2 is turned on prior to the switch S1, according to a normal sequence of power sources. In FIG. 13A, the switch S1 is opened, and the switch S2 is closed to apply a voltage -Vss to the parasitic circuits. Since the voltage -Vss, which is a reverse voltage, is applied to the p-type substrate, current does not flow in the parasitic circuit. That is, the negative voltage -Vss is applied to the base of the transistor Q3, as shown by the arrow V, and a ground potential, which is the reference potential Vref (potential 0), is applied to the emitter of the transistor Q3, as shown by the arrow U. Thus, the junction between the base and the emitter is in a reverse bias state, so current does not flow from the base to the emitter. The junction between the collector and the emitter of the parasitic npn transistor Q3 is in a non-conductive state. Hence, the parasitic circuit does not have any influence on the designed circuit, and the designed circuit operates as expected. Further, when the switch S1 is closed, the designed circuit enters a normal operational condition.
FIG. 13B shows an abnormal case where the switch S1 is turned on prior to the switch S2, which is a reverse sequence for applying the voltages. In FIG. 13B, the switch S1 is open, and the switch S2 is closed to apply the voltage +Vdd to the circuit. At this time, the p-type substrate is at a high electric potential compared to the reference potential Vref. A current flows from the voltage +Vdd to the ground as shown by an arrow W, through the resistors R4 and R5, the parasitic transistor Q5, parasitic resistors R3 and R2, and the base and the emitter of the parasitic npn transistor Q3. As a result, a path between the collector and the emitter of the parasitic npn transistor Q3 becomes conductive, and the electric potential of the base of the parasitic pnp transistor Q4 decreases.
Therefore, the current flows from the emitter to the base of the parasitic pnp transistor Q4 as shown by an arrow X, the path between the emitter and the collector of the parasitic pnp transistor Q4 becomes conductive, and the current flows from the base to the emitter of the parasitic npn transistor Q3, as shown by an arrow Y. Once this condition is achieved, the currents flow continuously through the transistors Q4 and Q3 as shown by arrows Y and Z, even if the current flow shown by an arrow W stops. As a result, the current path becomes warm, and elements might deteriorate or be damaged, which is referred to as a latch-up. Hence, normal operation cannot be ensured when the switch S2 is closed. In this manner, if the sequence for supplying the voltage is different from the normal sequence, problems could occur as explained above.
However, it is understandable that this kind of problem does not occur if the electric potential of the substrate Is maintained at the reference potential Vref, that is, the minimum electric potential. In other words, in FIG. 13B, if the substrate voltage is lower than around +0.3V, the current between the base and the emitter of the parasitic npn transistor Q3 hardly flows, and thus it seems possible to avoid problems such as explained above. However, the occurrence of the latch-up phenomenon depends on the pattern layout of the respective circuit elements, electric characteristics, and ambient temperature characteristics. Therefore, the pattern layout has to be designed with enough caution, just as in the conventional layout. If the switch S1 and the switch S2 are closed simultaneously, whether the latch-up phenomenon will result depends on the circuits, the pattern layout, and the electric characteristics of the elements.
As described above, when power is supplied to a monolithic semiconductor circuit which requires different DC voltage power sources, special attention is needed when turning on or turning off the power sources. If the substrate potential is unstable in a circuit with bipolar elements, the parasitic elements activate, depending on the layout of elements or circuit construction, which causes an abnormal current. As shown in the frames drawn with the dashed line in FIG. 13A or FIG. 13B, even in a simple circuit which is designed from resistors R4 and R5, and an npn transistor T3, a more complex circuit is secondarily formed by parasitic elements. In order not to active these parasitic elements, it is necessary to constantly maintain the electric potential of the substrate at the minimum electric potential. In order to maintain the electric potential, special attention is needed so that the electric potential of the substrate does not rise when the pattern layout is designed. If not, there is a possibility that the parasitic elements will be activated. In the frames drawn with double dot dash lines in FIGS. 13A and 13B, the parasitic circuit formed by the parasitic transistors Q1 and Q5 is similar to the previously described parasitic circuit formed by pnp transistor Q4 and npn transistor Q3. Therefore, when the electric potential of the substrate rises locally, excessive current may flow into the elements and even into the bipolar circuit.
As shown in FIGS. 11A-11F, when a plurality of circuits are formed on the same substrate, when voltages are supplied to a semiconductor integrated circuit using a p-type substrate (or an n-type substrate), it is preferable to apply a voltage -Vss prior to applying +Vdd (or +Vdd prior to -Vss). When disconnecting the voltage, it is preferable to disconnect voltage +Vdd prior to disconnecting voltage -Vss (or -Vss prior to +Vdd). FIG. 14A and FIG. 14B are timing charts showing a desired sequence of the turning on and turning off, and FIG. 15A and FIG. 15B are timing charts showing an undesired sequence of the turning on and turning off.
As described above, FIGS. 13A and 13B show circuits where a circuit 1 in FIG. 11A corresponds to a CMOS circuit comprising T1 and T2, a circuit 3 corresponds to a bipolar circuit comprising T3. As explained above, FIG. 13A illustrates a normal conventional power source voltage supplying sequence, while FIG. 13B illustrates an abnormal conventional power source voltage supplying sequence. Electrically, it is noteworthy that current flows from the base to the emitter of the parasitic npn transistor Q3 in the parasitic circuit in FIG. 13B, that is to say, the path between the collector and the emitter of the parasitic npn transistor Q3 becomes conductive, while current does not flow from the base to the emitter of the parasitic npn transistor Q3 in the parasitic circuit in FIG. 13A.
Abnormal current in the parasitic element is caused when the substrate electric potential exceeds the reference potential Vref. Especially when a silicon substrate is employed, once the substrate electric potential exceeds the reference potential Vref by the amount of a forward voltage (for example, about 0.7V), enough current to activate the parasitic circuit starts flowing. Thus, it is important to maintain the value of the substrate electric potential at a low level.
As explained above, a conventional semiconductor integrated circuit requires different direct current power sources. In such circuits, if the on-off sequence of the power supply sources is incorrect, some semiconductor integrated circuits suffer serious problems, such as deterioration or damage. In the past, in order to avoid such deterioration or damage from an abnormal current occurrence, the power source comprises a voltage on-off circuit. However, the voltage on-off circuit is very complicated, which makes the power source circuit expensive.